PCB DESIGN SERVICES & LAYOUT OrCAD OrCAD CAPTURE & OrCAD PCB LAYOUT PADS PADS PCB LAYOUT CADENCE ALLEGRO CADENCE ALLEGRO PCB LAYOUT MENTOR BOARD STATION LAYOUT PCAD LAYOUT CR-5000 LAYOUT FLEX BOARDS FABRICATION & ASSEMBLY ON-SITE SENIOR PCB DESIGNERS PRICING STRUCTURE INTAKE DOCUMENT SIGN-OFF SHEET ALTIUM DESIGN TRAINING REQUEST A QUOTE
iLearn PCB Layout PCB TRAINING SCHEDULE OF CLASSES DVD TRAINING SERIES NEW! E-INSTRUCTION TRAINING OrCAD PADS TRAINING CADENCE ALLEGRO EMC TRAINING SPECCTRA AUTOROUTER MENTOR GRAPHICS NEW SYSTEM INSTALLATION PRICING STRUCTURE ALTIUM DESIGN TRAINING PSPICE TRAINING
ABOUT I-LEARN PCB iLearn PCB Layout DEMO MEETING SIGN UP
PRESS RELEASES MONTHLY NEWSLETTER ITAR CERTIFICATION
FABRICATION & ASSEMBLY REQUEST A QUOTE ARTICLES LINK TO US

PRINTED CIRCUIT BOARD DESIGN SERVICE BUREAU

Design Tips and Articles


Vias And Their Effects In Solid Power Planes

Use of vias in solid power planes will decrease the total planar capacitance based on the number of vias and the amount of real estate that has been etched out from the planes. A capacitor works by virtue of energy storage that is contained within a metallic structure. With less metal (copper plane), the current density distribution is decreased. As a result, less area exists to support the number of electrons that create the current density distribution. The figure below illustrates the value of capacitance between parallel power planes in two configurations: solid power planes and power planes with 30% of the area removed by vias and clearance pads.


Sign up to receive a copy of our
2007 Schedule of Classes and Pricing

Email: