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Hidden Characteristics of Digital Components
When selecting components for a particular application, design engineers are generally interested only in functionality, operating speed, and propagation delay of the internal logic gates as published by the manufacturer in their datasheets. Consideration of electromagnetic effects is seldom performed.
As digital components become faster (decrease in internal propagation delay between transistors), an increase in RF current, crosstalk, and ringing may occur, based on the inverse relationship between speed and EMI. A device is generally chosen based on the propagation time from input to output, along with the setup time of the input signal. Almost all components have internal logic that operates at a faster edge than required for functionality. Consequently, slower logic families (internal gates) are preferred for minimizing EMI and signal integrity problems, which is contrary to design specifications based on requirements mandated by marketing and design engineers.
One extremely important device parameter that device manufacturers do not usually specify in data sheets is peak inrush surge current into the device operating under maximum capacitive load. Peak surges are the result of logic crossover currents, device capacitive overheads, and transmission line (trace) capacitance. Input surge current may exhibit levels that are many multiples of the actual signal currents driven, and it can be as much as ten times quiescent levels!
When we propagate an electromagnetic field down a transmission line, dc current is required to charge the load(s). These loads will always be capacitive. Drive current must come from somewhere. This somewhere is the power distribution network through the component from input pin to output. Thus, if a device sources 25 mA to a load, this 25 mA is added to the quiescent or steady-state current rating of the component. This current surge lasts a brief period, whereas the quiescent value is always constant. If there are ten drivers, up to 250 mA of current may be consumed from the power distribution network, in addition to quiescent current. Few engineers recognize this fact because it is rarely published in data sheets.
When selecting a logic family, manufacturers will specify in their data books the "typical or maximum" edge rate, travg or trmax for clock and I/O pins. Generally, this specification is usually 2–5 ns maximum. It is observed that the "minimum" edge rate, trmin, is rarely provided. A device with a 2-ns typical edge rate specification may in reality have a 0.5 to 1.0-ns edge rate, either rising or falling. The greatest contributor to RF energy is the edge rate transition, not actual operating frequency! A 5 MHz oscillator driving a 74F04 (with a 1 ns edge) will generate larger amounts of RF spectral energy than a 50 MHz oscillator driving a 74ALS04 (with a 4-ns edge). This one component specification is the most frequently overlooked and forgotten parameter in PCB design; however, this is a design engineer’s most critical concern to ensure an EMI compliant product. This is a frequency domain issue (EMI), not time domain (signal integrity).
The frequently heard statement, "Use the slowest logic family possible" goes back to the component manufacturer's failure to specify or publish minimum edge rate parameters in their data books.
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